HDL Entry EASE ver. 6.0 R10

Posted By: webgurru
HDL Entry EASE ver. 6.0 R10

HDL Entry EASE ver. 6.0 R10 | Win32 | 14,80 Mb

EASE offers the best of both worlds with your choice of graphical or text based HDL entry. You don’t need to be a master of either Verilog or VHDL. When you're creating a new design, just enter your design using your mix of graphics and text. EASE automatically generates optimized HDL code for you in your preferred language - VHDL or Verilog. Industry standard version control environments deal with design and configuration management enabling multiple users to work simultaneously on one EASE project.

What's new in the 6.0 Release

In EASE™

Major items:

* HTML Generation
Generates HTML for the whole project with scalable and linked graphics, project contents and generated HDL files.

* HDL Ware dialog
Library with parameterized standard building blocks like adders, counters, comparators and shifters

* Vendors / Tools / Versions dialog Global approach to declaring which tools and versions of simulator, synthesis and FPGA tools are present in your environment and selecting an active version for your project.

* IP integration
Generate component symbols on the fly from Verilog or VHDL files for Vendor specific models like LPM's.

* Core Generator dialog
Dialog to start FPGA specific core generator and import the generated VHDL or Verilog core.

* Improved HDL Import
Import does now allow to specify how to import objects and to re-import objects and adjust their interface.

* Drag & Drop from the browser to
Instantiate components in the diagram window Move entities, modules or packages to another library.

* Port declarations:
Delete through hierarchy
Add through hierarchy
Copy inverted mode to other block (with SHIFT key)
Support type conversion functions in component port map.

Diagram Editors:

* Short cuts (accelerators) for button functions.
(Multiple selection of ripper will rotate ripper side)
* Ripper dialog to edit all rippers of a net.
* Net highlighting to find everything connected and survive undo/redo actions.
* Improved graphical representation for nets which do not have an HDL equivalent.
* Added Label submenu in object popup menu to access the label Properties and Restore Default location.
* Display of port/net/generic type.
* Show rubber boundaries of objects that need to be on grid snapped to the grid.

Miscellaneous:

* Add standard packages to project if needed during import.
* Allow disable of synthesis pragmas in user package properties
* Single dialog to create new entity/component
* Added support for Verilog primitives (also in Verilog import)
* Moved PortOrder definition from Project to Entity
* Allowed multiple selections of entities in library purge.
* Range checking for nets/ports/rippers (simple ranges only).
* Added warning for nets with only one connection.
* HDL Menu added
* Show different cursor when copying objects.
* Label rotation 90 / 270 in opposite direction.



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WebGurru