Verilog HDL: A Guide in Digital Design and Synthesis
# Author: Samir Palnitkar
# Paperback: 448 pages (February 2003)
# Publisher: Prentice Hall PTR
# Language: English
# ISBN: 0130449113
|“||The complete Verilog HDL reference progresses from the basic Verilog concepts to the most advanced concepts in digital design.|
Presents a logical progression of Verilog HDL-based topics.
Covers the gamut of Verilog HDL fundamentals, such as gate, RTL, and behavioral modeling, all the way to advanced concepts, such as timing simulation, switch level modeling, PLI, and logic synthesis.
For Verilog HDL digital IC and system design professionals. Verilog HDL is a language for digital design, just as C is a language for programming. This complete Verilog HDL reference progresses from the basic Verilog concepts to the most advanced concepts in digital design. Palnitkar covers the gamut of Verilog HDL fundamentals, such as gate, RTL, and behavioral modeling, all the way to advanced concepts, such as timing simulation, switch level modeling, PLI, and logic synthesis. Verilog HDL is a hardware description language (with a user community of more than 50,000 active designers) used to design and document electronic systems. This completely updated reference progresses from basic to advanced concepts in digital design, including timing simulation, switch level modeling, PLI, and logic synthesis.
Samir Palnitkar is President and CTO of Integrated Intellectual Property Inc. (I2P).
With a Foreword by Prabhu Goel, written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective of Verilog rather than emphasizing only the language aspects. The information presented is fully compliant with the IEEE 1364-2001 Verilog HDL standard. Among its many features, this edition: describes state-of-the-art verification methodologies; provides full coverage of gate, dataflow (RTL), behavioral and switch modeling; introduces you to the Programming Language Interface (PLI); describes logic synthesis methodologies; explains timing and delay simulation; discusses user-defined primitives; offers many practical modeling tips; and includes over 300 illustrations, examples, and exercises, and a Verilog resource list. Learning objectives and summaries are provided for each chapter. The CD-ROM contains a Verilog simulator with a graphical user interface and the source code for the examples in the book. What people are saying about Verilog HDL - "Mr.Palnitkar illustrates how and why Verilog HDL is used to develop today's most complex digital designs. This book is valuable to both the novice and the experienced Verilog user. I highly recommend it to anyone exploring Verilog based design." - Rajeev Madhavan, Chairman and CEO, Magma Design Automation. "This book is unique in its breadth of information on Verilog and Verilog-related topics. It is fully compliant with the IEEE 1364-2001 standard, contains all the information that you need on the basics, and devotes several chapters to advanced topics such as verification, PLI, synthesis and modeling techniques." - Michael McNamara, Chair, IEEE 1364-2001 Verilog Standards Organization. This has been my favorite Verilog book since I picked it up in college. It is the only book that covers practical Verilog. A must have for beginners and experts." - Berend Ozceri, Design Engineer, Cisco Systems, Inc. "Simple, logical and well-organized material with plenty of illustrations, makes this an ideal textbook." - Arun K. Somani, Jerry R. Junkins Chair Professor, Department of Electrical and Computer Engineering, Iowa State University, Ames.