This book is a compilation of selected papers from 2023 DigitalFUTURES — The 5nd International Conference on Computational Design and Robotic Fabrication (CDRF 2023). The work focuses on novel techniques for computational design and robotic fabrication. The contents make valuable contributions to academic researchers, designers, and engineers in the industry. As well, readers will encounter new ideas about understanding intelligence in architecture.

A systematic computer-aided approach provides a versatile setting for the control engineer to overcome the complications of controller design for highly nonlinear systems. Computer-aided Nonlinear Control System Design provides such an approach based on the use of describing functions. The text deals with a large class of nonlinear systems without restrictions on the system order, the number of inputs and/or outputs or the number, type or arrangement of nonlinear terms. The strongly software-oriented methods detailed facilitate fulfillment of tight performance requirements and help the designer to think in purely nonlinear terms, avoiding the expedient of linearization which can impose substantial and unrealistic model limitations and drive up the cost of the final product.

Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail.

In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay testing. Fueled by the above events, a tremendous growth has occurred in the research on delay testing. Recent work includes fault models, algorithms for test generation and fault simulation, and methods for design and synthesis for testability. The authors of this book, Angela Krstic and Tim Cheng, have personally contributed to this research. Now they do an even greater service to the profession by collecting the work of a large number of researchers. In addition to expounding such a great deal of information, they have delivered it with utmost clarity. To further the reader's understanding many key concepts are illustrated by simple examples. The basic ideas of delay testing have reached a level of maturity that makes them suitable for practice. In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech­ niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest.

As the feature size decreases in deep sub-micron designs, coupling capacitance becomes the dominant factor in total capacitance. The resulting crosstalk noise may be responsible for signal integrity issues and significant timing variation. Traditionally, static timing analysis tools have ignored cross coupling effects between wires altogether. Newer tools simply approximate the coupling capacitance by a 2X Miller factor in order to compute the worst case delay. The latter approach not only reduces delay calculation accuracy, but can also be shown to underestimate the delay in certain scenarios.

Statistical timing analysis is an area of growing importance in nanometer te- nologies‚ as the uncertainties associated with process and environmental var- tions increase‚ and this chapter has captured some of the major efforts in this area. This remains a very active field of research‚ and there is likely to be a great deal of new research to be found in conferences and journals after this book is published. In addition to the statistical analysis of combinational circuits‚ a good deal of work has been carried out in analyzing the effect of variations on clock skew. Although we will not treat this subject in this book‚ the reader is referred to [LNPS00‚ HN01‚ JH01‚ ABZ03a] for details. 7 TIMING ANALYSIS FOR SEQUENTIAL CIRCUITS 7.1 INTRODUCTION A general sequential circuit is a network of computational nodes (gates) and memory elements (registers). The computational nodes may be conceptualized as being clustered together in an acyclic network of gates that forms a c- binational logic circuit.

From a review of the Second Edition
'If you are new to the field and want to know what "all this Verilog stuff is about," you've found the golden goose. The text here is straight forward, complete, and example rich -mega-multi-kudos to the author James Lee. Though not as detailed as the Verilog reference guides from Cadence, it likewise doesn't suffer from the excessive abstractness those make you wade through. This is a quick and easy read, and will serve as a desktop reference for as long as Verilog lives. Best testimonial: I'm buying my fourth and fifth copies tonight (I've loaned out/lost two of my others).'
Zach Coombes, AMD

The building blocks of today's and future embedded systems are complex intellectual property components, or cores, many of which are programmable processors. Traditionally, these embedded processors mostly have been pro­ grammed in assembly languages due to efficiency reasons. This implies time­ consuming programming, extensive debugging, and low code portability. The requirements of short time-to-market and dependability of embedded systems are obviously much better met by using high-level language (e.g. C) compil­ ers instead of assembly. However, the use of C compilers frequently incurs a code quality overhead as compared to manually written assembly programs. Due to the need for efficient embedded systems, this overhead must be very low in order to make compilers useful in practice. In turn, this requires new compiler techniques that take the specific constraints in embedded system de­ sign into account. An example are the specialized architectures of recent DSP and multimedia processors, which are not yet sufficiently exploited by existing compilers.

On Integration computer applications have by now entered almost all enterprises, but mostly in an uncoordinated way without long term integration plans or automation strategies. Departments introduced computing equipment and purchased or developed programs to support their department operations. This approach divided an enterprise into small and almost autonomous enterprises, each with the goal to deploy the computer to make their department and its associated activities work more efficiently. Thus many departments acquired computers, developed and installed automation systems and PCs and educated their staff, announcing this was done to make the work force aware of the large benefits that computers bring. In this fashion the most important functions in an enterprise were more or less computerized (accounting more, CAM and CAD less). In 1986 Europe, the level of computerization in descending order of significance was as follows: Accounting, Inventory Control, Order Entry, Production Planning & Control, Purchasing, Distribution, Sales Planning, Shop Floor Control, Process Control, Quality Control, Manufacturing Engineering (including CAM), and finally Design Engineering (with CAD) [1].

This is the fourth book from the Series "Scientific Fundamentals of Ro­ botics". The first two volumes have established abackqround for studying the dynamics and control of robots. While the first book was exclusive­ ly devoted to the dynamics of active spatial mechanisms, the second treated the problems of the dynamic control of manipulation robots. In contrast to the first two books, where recursive computer-aided me­ thods for setting robot dynamic equations where described, this mono­ graph presents a new approach to the formation of robot dynamics. The goal is to achieve the real-time model computation using up-to-date mi­ crocomputers. The presented concept could be called a numeric-symbolic, or analytic, approach to robot modelling.

Hardware Design and Petri Nets presents a summary of the state of the art in the applications of Petri nets to designing digital systems and circuits. The area of hardware design has traditionally been a fertile field for research in concurrency and Petri nets. Many new ideas about modelling and analysis of concurrent systems, and Petri nets in particular, originated in theory of asynchronous digital circuits. Similarly, the theory and practice of digital circuit design have always recognized Petri nets as a powerful and easy-to-understand modelling tool..

This book is a compilation of selected papers from 2023 DigitalFUTURES — The 5nd International Conference on Computational Design and Robotic Fabrication (CDRF 2023). The work focuses on novel techniques for computational design and robotic fabrication. The contents make valuable contributions to academic researchers, designers, and engineers in the industry. As well, readers will encounter new ideas about understanding intelligence in architecture.

This book offers a comprehensive review of smart technologies and provides perspectives on their applications in urban engineering. It covers a wide range of applications, from manufacturing engineering and transport logistics to information and computation technologies, providing readers with fresh ideas for future research and collaborations.

This book was motivated by the problems being faced with shrinking IC process feature sizes. It is well known that as process feature sizes shrink, a host of electrical problems like cross-talk, electromigration, self-heat, etc. are becoming important. Cross-talk is one of the major problems since it results in unpredictable design behavior. In particular, it can result in significant delay variation or signal integrity problems in a wire, depending on the state of its neighboring wires. Typical approaches to tackle the cross-talk problem attempt to fix the problem once it is created. In our approach, we ensure that cross-talk is eliminated by design. The work described in this book attempts to take an "outside-the-box" view and propose a radically different design style. This design style first imposes a fixed layout pattern (or fabric) on the integrated circuit, and then embeds the circuit being implemented into this fabric. The fabric is chosen carefully in order to eliminate the cross-talk problem being faced in modem IC processes. With our choice of fabric, cross-talk between adjacent wires on an IC is reduced by between one and two orders of magnitude. In this way, the fabric concept eliminates cross-talk up-front, and by design. We propose two separate design flows, each of which uses the fabric concept to implement logic. The first flow uses fabric-compliant standard cells as an im­ plementation vehicle. We call these cells fabric cells, and they have the same logic functionality as existing standard cells with which they are compared.

Problems, methods and algorithms of decision making based on an uncertain knowledge now create a large and intensively developing area in the field of knowledge-based decision support systems. The main aim of this book is to present a unified, systematic description of analysis and decision problems in a wide class of uncertain systems described by traditional mathematical models and by relational knowledge representations. A part of the book is devoted to new original ideas introduced and developed by the author: the concept of uncertain variables and the idea of a learning process consisting in knowledge validation and updating.