Cadence Virtuoso version IC6.1.6 ISR8
Cadence Virtuoso version IC6.1.6 ISR8 | 9.7 Gb
Cadence Design Systems, Inc., the leader in global electronic design innovation, announced the availability of the update (IC6.1.6 ISR8) to its next-generation Cadence Virtuoso custom IC design platform. Cadence continues to provide a complete solution enabling customers to design custom integrated circuits reliably and with a high level of productivity. This latest release incorporates new technology as well as significant performance improvements in existing technology, offering advanced solutions for the custom design of chips proven in production by dozens of customers.
- Cadence Virtuoso version IC6.1.6 Base
- Cadence Virtuoso version IC6.1.6 ISR8 Hotfix
- CMOS Circuit Design, Layout, and Simulation, 3rd Ed. pdf
- CMOS Mixed-Signal Circuit Design, 2nd Ed. pdf
- Cadence Virtuoso version IC6.1.6 ISR8 Hotfix
- CMOS Circuit Design, Layout, and Simulation, 3rd Ed. pdf
- CMOS Mixed-Signal Circuit Design, 2nd Ed. pdf
CCRs Fixed in ICADV12.1 ISR10 and/or IC6.1.6 ISR8
Note: This is a collated list of CCRs that were fixed in one or both of the aforementioned releases.
CCR
Number TITLE
––––––––––––––––––––––––––––––––––––––––––––-
CCR Reviewed_Titles
1309403 itkDB_pic.a does not appear to be compiled correctly
1305285 AltGr key not recognized by text editor
1304908 UNL errors out with leqp can't handle (nil <=4) error message in IC6.1.6 ISR7
1303895 The dbCopyCellView operation aborted due to failure of the Cadence Design Framework II license feature in the latest ISR
1303467 SMG SV-AMS netlisting resolving pin name to scientific notation number
1303080 How to get Connectivity on Flat VIA Shapes
1301781 retainStateSettings causing to load Cell based options for UNL
1301592 SMG SV-AMS netlisting real bus as packed array
1301543 Unable to close Virtuoso because ADE load state caused dbClose invalid cellView error
1301478 SMG to handle expressions with metric suffixes while generating SystemVerilog UDTs
1301173 Virtuoso Text Editor: Using an AZERTY French keyboard, Alt Gr key is not working
1300945 Importing the same Verilog file twice gives error VERILOGIN-324
1300128 veriloga text editor fails to handle composed keys
1298752 Mosaic instance Bbox is changed when using Use True BBox option
1297235 Segmentation fault occurred during Abstract generator in IC6.1.6
1297029 Cannot use mouse scroll wheel to change Via Row/Column field in Property Editor in IC6.1.6 ISR7
1296486 OASIS_Simulation_Interface license error leads to incorrect result in SGE distributed Parametric simulation
1296368 Copy library not referencing new library cells.
1296220 Request of EAD setup loading time improvement
1295804 vfoGuardRing.ils is not automatically loaded by 'virtuoso -nograph'.
1295745 VPS: Importing of results missing all the parasitics in the result form
1295592 emirreport gives failed to run command line error for EM
1295370 Blank Edit Object Properties form
1293281 DRD misses some minExtensionToCorner spacing violations
1293051 Cannot change width mode consistently in IC6.1.6 ISR6
1292884 Create Via Form: Unable to change via justification (center-center) in Width/Height Mode
1292881 DRD no longer detects minExtensionToCorner spacings
1292793 ADE XL cannot retain job policy assignment on the test that is not selected
1292548 Fit Y to Visible X has wrong functionality
1292440 EAD high precision extractor does not calculate total resistance correctly
1292382 Exactly overlapping shapes in different hierarchy should be treated as one by Pad Opening Info
1291775 For advanced processes, the EAD extractor is not checking for vertically overlapping shapes
1291176 MPS_ERROR when using EAD with third-party simulator
1290357 Performing yank and paste using SKILL code in IC6.1.6 ISR6 yields different results from previous IC6.1.x versions
1290173 dptReColor() indefinitely activates and deactivates coloring engine in loop
1289951 Received *Error* difference: can't handle (nil - 2) when open a new library from CIW File -> New -> Library
1289886 Placement Planning does not insert cap cell
1289869 addToExportList causes Virtuoso to crash
1289527 Display name for 'groundCap' parameter is 'Decoupled Capacitance' for Max Capacitance constraint.
1289132 EAD cannot read EM Data File format as same as VPS correctly
1288689 DRD Compactor crashes with small bus example
1288371 router crashes when setting rdeEval("setvar db.ignore_layers CSP")
1288358 DRD checker not checking for minExtensionEdge rule
1288055 Create Via claims: Mask numbers not as expected in std via def RX_sub
1288051 DPT recoloring claims: Mask numbers not as expected in std via def RX_sub
1287824 keepout errors post routing
1287789 eol spacing errors post routing
1287644 VPSML attempts to read EM rule file from an incorrect path
1287348 DRD compactor generates minCutClassSpacing violations
1287333 Overlapping pads counted twice in IC6.1.6 ISR6
1286955 ADE XL 12.1: Wrong job policy setting for inactive test
1286347 ignoreDesignChangesDuringRun not using global design variables with ams designer
1286161 Design analysis markers inadvertently removed from Annotation Browser when Routability Checker is run
1285985 VPSML and emirreport crash with 16FFp qrcTechFile
1285488 DPT GUI shows wrong color on the layers for stdVias in ICADV12.1 ISR8
1285430 emirreport issues when using autorun=true in post USR1 builds
1285268 Unable to visualize IDC current in EAD dataset for third-party simulator
1284805 vpsbatch does not finish em processing
1284644 Congestion Map should be affected from wide nets constraints
1284158 Random crashing when running check and save
1284146 In ADE XL, AMSD does not change model sections over corners when using ignoreDesignChangesDuringRun
1284093 VerilogOut: logical verilog does not work with the merge all option
1283724 In IC6.1.6, defout missing flattened vias
1283577 Data not properly populated in the "Waveform Signal" GUI when using amsDMV in conjunction with an ADE XL state with corners defined
1283079 CRASH: VSR crash when star_route called twice on same net with create_fromto
1282772 In IC6.1.6 ISR6, Virtuoso crashes while running distributed processing simulations in LSF mode
1282675 When AMS UNL views ADE XL simulation results, Irun log has suppressed compile and elaborate sections.
1282419 IC6.1.6: Virtuoso hangs at exit and CPU utilization hits 100%
1282066 Ability to turn off or ignore popup which comes when ignoreDesignChangesDuringRun is set and parameters exist
1281892 ncvlog illidn error with smg generated models
1281441 Router fails to route due to custom via definition for top layer
1281413 pteLoadFromTechFile causes selectability problems
1281351 QOR: getting multiple minWidth segments in star_route command.
1281121 stretch causes DRC violation
1280724 Wire Assistant doesn't appear with _iaGetOverrideEnabled error
1280678 incremental netlistAndRun after a netlist failure is not generating bindings for multiview cell
1280663 IC6.1.6 ISR6: Modgen recognizes the oaText
1280623 IC6.1.6 ISR6: Virtuoso crashes when using the Create Wire command
1280591 preRun trigger emission must occur before anything else in run flow
1280298 Router centers via1 on m1 pins causing DRC errors
1279996 VPS: Design resistors are listed under VSS pin in the EM report
1279908 runams with netlist command requires OASIS license
1279746 ADE XL crashes when copying and pasting multiple outputs
1279702 VPS is not able to process Recovery factor (em_recover) from ictfile
1279305 Copying of an expression to multiple expressions of another test leads to crash
1279279 Pin To Trunk routing results in long poly wire segments
1279122 Wire editing swaps "top" and "bottom" layers of wire assistant
1279071 Fast R extractor has some problems in the mesh wiring.
1278965 Provide ability to plot from Isignal icon in EAD results tab
1278961 If no tran analysis is run, we should not show Isignal in EAD results tab
1278498 Pin check for schematic has more pins than symbol with schematic switch master
1278477 Pin check for schematic has more bus pins than symbol
1278466 Pin check for schematic and text with more pins than symbol should fail at netlisting
1278411 Concat bus MM switchmaster functional gives false positive pin check
1278410 Concat with bit select switchmaster functional gives false positive pin check
1278397 Concat switchmaster functional gives false positive pin check
1278353 Provide SKILL API for Palette User Triggers
1277936 Virtuoso does not exit from CIW menu
1277891 crash in wsGraphSelectionState
1277877 DRD reports a dual pattern odd-loop on a Triple Patterning layer
1277870 The shielding constraint tandem (below) and coaxial should not use poly
1277530 VLS XL crash during generate all from source with extractor on
1277364 The waveform cannot be plotted when the wave name is 12345.trn.
1277152 Item selection callback is not working in IC6.1.6 if the callback function is defined within procedure.
1277090 DRD reports false twoWidths spacing violations causing the color engine to fail
1277064 libManager crashes if the cdslck files cannot be read
1276457 Auto Via Draw Area mode caused VLS hang
1276436 PIEA extraction should not stop with error CPF-1615
1275818 P2T routing with pin strapping causes DRC violation
1275565 Layout connectivity extractor should ignore stampLabelLayer function and mask number
1275323 Generic modgen routing is not inserting vias in few areas of the MODGEN routing
1275315 PreCreateObj triggered for ddViewFileType after ddCreateObj has been canceled
1275313 Routing IDE warning: Mask numbers not as expected in std via def RX_sub
1274830 Abstract is changing scan sigType to signal during pins step
1274016 VSR does not complete routes when there are blockages of type 'fill'
1273483 Reinitialize does not change modgen to status placed
1272999 rapidIP3 from AC analysis plot shows all power points
1272951 Setting the accessEdgesOn variable causes excessive memory use when panning
1272794 PIEA extraction takes very long with pushPGNetTypes enabled
1272670 GENERIC section not printed by VHDL netlister when hnlVHDLExternalDirList is used
1272007 Virtuoso Layout crashes when DRD form accessed
1271662 Quick Align fail for T-type path when auto-merge is allowed in any stretch like operation
1271507 bus_route does not complete routing on this bus
1271106 Via alignment to wire edge not obeyed in some cases
1271021 In IC6.1.6_ISR6, All Pins Optimization gives incorrect error about not enough space
1270769 DRD fails to correctly display minCutClass spacing violations
1270761 DRD rule text is always unreadable
1270620 proute_via_insertion results in minEdge failures
1270586 Update Components and Nets caused Modgens to move
1270547 Circuit Prospector filter for (un)constrained objects does not work properly
1270464 Sensitivity Analysis for uniform distribution models only uses half the specified range
1270186 tracef(t) produces extra information in IC6.1.6 release
1270161 Give more meaningful error message for HspiceD
1269762 In VLS XL, probe with Bus Bits Net Class is not highlighted
1269654 Crash when routing Point-to-Point with Color Track Patterns
1269590 Pin to Trunk router creates DRC violations if pre-placed vias or MPPs on pins already exists
1268817 data.dm in destination library is left in Checked Out state after copying a cell under SOS environment
1268569 Voltage source region cannot be created due to /tmp/ZeroDropInst file
1268532 Stretch FGR results in an unexpected location
1267690 noiseSummary command is not creating the noise summary file
1267333 The Results - Violations Display command hangs ADE environment
1267207 Some source fromtos created with minWidth during star routing
1267093 Cover obstruction on lower layers prevents the router from seeing shapes on upper layers
1266776 UNL: Improve the error message that appears when an invalid AMS simulator option is specified in ADE results
1266758 VPSML Connecting lines between violation markers are missing in IC6.1.6 ISR6
1266692 OASIS_Simulation_Interface license error
1266552 Improve the tapering at sink instance pin during star routing
1266192 Extend verilogIn maximum port size
1265785 Create autoVia with viaFillEnclosureOverlap ON did not fill up the overlapped area
1265754 Enhance Layer Palette search filter to scroll to the selected active layer automatically
1265135 stimulus file cannot be found using AMS designer and environment variable
1265058 vsabatch cannot copy the complete database to a result directory for vsaplot display
1264886 differences in check_routing_shape and check_vias results for allowedCutClass constraint checking
1264650 STAR routing to handle multiple pins/shapes per terminal
1264167 saveGraphImage does not wait for plotting to be displayed completely
1264112 In IC6.1.6, batch job fails if no "res=" values in emDataFile
1263977 pR-view bug for the current colorMap bar
1263845 modgen instances are placed offgrid with respect to global grid when mirrored
1263478 Cannot return to top layout by using Edit->Hierarchy->Return
1263156 Getting "*Error* system: operating system error occurred in execl: 7" error on displaying netlist
1262483 Via alignment is switched to center-center after Stretch command
1262399 power via insertion failing in hierarchical mode
1261253 VPS L attempts to checkout VPS XL license at 28nm EM analysis
1260974 viewing depth option should support negative depth
1260531 Use consistent terminology in all 'Function' rows and columns"
1260022 VCP is not placing instances whose masters do not have any geometry other than prBoundary
1260013 support triple height standard cell or more in VCP
1260007 An internal error on invoking reshape
1259971 The Create Via form retains the value of the Filter field
1259210 pull down and pop-up menus disappear when moving the mouse
1258960 Order of attribute of Edit Cellview Properties form should be lib/cell/view
1258791 AutoVia feature creates spacing violations for intermediate layers
1258298 vfo file load issue - CDLOut/ 3rd party tools .ils files are order dependent
1258240 CPF import miss gnd netSets
1257808 Virtuoso hangs after hiQuit()
1256468 ADE XL: result of Violations Display is incomplete when the Print command is clicked twice
1256391 Unexplained layerStackIsValid warning for mimcap layers
1254813 ADE not saving changes to Additional Arguments field in ADE L state
1253511 Syntax error on parsing emDataFile: Unexpected '='
1252565 Cannot create a Stack Via with more than 1000 rows
1252151 Crash after ADEXL-1625 message
1251037 all twigs on one instTerm need to be routed
1250094 SMG not generating the model for single index name at the instance pin
1248139 Need module name update for text cellviews when Update Instances is used
1247004 modify DRD to handle minArea and minRectArea
1246637 Create autovia with Extend Enclosure Beyond Overlap option caused edge length DRC violations
1246261 VPS to validate the input requirements
1246162 Changing the user or effective CDF is changing the base CDF also
1245930 verilogIn imports schematic OK first time; errors when run second time
1245697 Bindkey not working when Customize Range of Set Range section is set to min value & max value
1245692 Zoom-In of vsaplot should display all the data of specified region
1245632 vfpCPHGenPhysicalHierNoPropFile() should not generate unplaced instances
1245106 vsaplot should support results display same as results window
1244000 "Auto Via should merge the overlap area and then partition and fill the via
1243951 Modify Corner for chamfer on rectangle shapes in 16nm created non-45 angles
1243639 Need an option to control merging during Autovia generation
1243315 viaTriggers not working accurately
1241852 DRD reports sameMask spacing violations on stitched fixed loops
1241763 simulation tool environment settings cause context file to be loaded incorrectly.
1241718 Schematic property form gets updated with values from layout property form
1240577 VPS ML: Markers on layout disappear when zooming in
1239001 Checker is flagging false errors in 16nm data
1237164 Multipart path not redrawing with multiple edits in SKILL
1236617 Unable to retrieve corner/sweep point data with pss/pnoise in ADE XL
1236129 OASIS_Simulation_Interface license error when using Spectre simulator from ADE
1235993 asterisk(*) at the beginning of the parameters line in the spectre netlist causes errors
1235599 Routability Checker needs option to flag pins on incorrect side of prBoundary for selected routing direction
1234892 When Modgen is created in the schematic, trunks inside Modgen are decomposed
1233314 Trunk to Trunk is slow
1233289 Trunk to Trunk connects to twig metal, not to trunk
1231683 OASIS_Simulation_Interface license error when using Spectre simulator from ADE
1228387 Minimum requirement for metals is smaller than the actual metal width for errors
1227523 leEditInPlace command deletes VLS XL Gen From Source data
1227020 Unable to plot in PSFXL format during simulation with compression ON
1225109 Missing CDF Parameters in Edit Object Properties form
1224283 Cannot plot from ADE XL for AMS with Save times
1221334 ampersand used in CDF parameter prompt is displayed as amp; in Edit Object Properties form
1220633 Router fails to plan channels properly when constraints require mix of widths
1216301 update_power_domain specified incorrectly in exported CPF
1216295 PG nets not read completely from CPF
1212948 Even if the Route option is enabled, Routing is not done when the Generic Modgen is created.
1210593 ADE XL deletes contents of test editor if simulation fails
1200651 VSR router creates redundant vias over existing connections
1200385 Missing CDF Parameters in Edit Object Properties Form
1199726 DRD detects false twoWidths spacing violations
1199087 amsDMV unable to open results dumped by pure digital simulation
1197493 ADE XL crashes when copying and pasting multiple outputs
1195392 Signal name mapping issue when signal name prefix is the same as the top level testbench
1195199 Specifying 10K instances for mismatch crashes ADE XL Monte Carlo
1191768 CV2CV generates illegal terminal name for functional view.
1186752 Finish wire makes extra extension with taper pin width option
1182890 QoR issues with Modgen pin to trunk router
1179637 VHDL Toolbox netlisting fails with ".:schematic' is not a stopping cell"
1172401 create wire results in minEdgeAdjacentLength violation during via addition
1171978 Cluster and Modgen generated guardring based on different layer
1167850 Create Via creates allowedWidthRanges violations because of 1000 dbuPerUU
1159467 saveGraphImage has incorrect zoom
1158078 Changing the pattern changes the spacing between rows
1091554 Netlist not created for MonteCarlo with DUT and simulation remains in pending status
1090946 VLS XL Update Schematic Parameters destroys some field of the Edit Properties Form (schematic side)
1082020 useTrueBBox is not effective for mosaic
1072567 ADE XL Monte Carlo Specify Instances for Mismatch Generates Bad Netlist / Virtuoso: free(): invalid pointer
1054842 adding "selectable Contact Rows" as an option to "Guard Ring Options" UI
1045083 Copy cell with Update Instances ON does not update the module name
1034623 Via maximization is not effective
1029397 Waveform snapshot is broken when CPU is highly used
988260 Incorrect Via center calculation
971060 Edit Object Properties form: CDF parameter fields goes blank
918144 Schematic Property Editor is not displaying the CDF parameter section
915930 /tmp/.X11-unix/X file is not removed sometimes
855908 Edit Object Properties form goes blank when Update Layout Parameters command is run on a symbol
718511 Missing component properties in schematic window
611368 CDF missing from Edit Object Properties form
601269 Edit Object Properties form - CDF section is blank
519711 Schematic query form corrupted when layout query form open
474082 Blank CDF panel in schematic Object Properties form
472258 request to document schCleanObjectProp function
469685 CDF parameter is not displayed in schematic properties form
427821 VLS XL Cross probing results in missing CDF in Schematic Property Editor
262971 The CDF parameter is not updated correctly.
190272 Schematic Property Editor data getting updated to layout
42580 CDF parameters in the Edit Object Properties form disappear
Note: This is a collated list of CCRs that were fixed in one or both of the aforementioned releases.
CCR
Number TITLE
––––––––––––––––––––––––––––––––––––––––––––-
CCR Reviewed_Titles
1309403 itkDB_pic.a does not appear to be compiled correctly
1305285 AltGr key not recognized by text editor
1304908 UNL errors out with leqp can't handle (nil <=4) error message in IC6.1.6 ISR7
1303895 The dbCopyCellView operation aborted due to failure of the Cadence Design Framework II license feature in the latest ISR
1303467 SMG SV-AMS netlisting resolving pin name to scientific notation number
1303080 How to get Connectivity on Flat VIA Shapes
1301781 retainStateSettings causing to load Cell based options for UNL
1301592 SMG SV-AMS netlisting real bus as packed array
1301543 Unable to close Virtuoso because ADE load state caused dbClose invalid cellView error
1301478 SMG to handle expressions with metric suffixes while generating SystemVerilog UDTs
1301173 Virtuoso Text Editor: Using an AZERTY French keyboard, Alt Gr key is not working
1300945 Importing the same Verilog file twice gives error VERILOGIN-324
1300128 veriloga text editor fails to handle composed keys
1298752 Mosaic instance Bbox is changed when using Use True BBox option
1297235 Segmentation fault occurred during Abstract generator in IC6.1.6
1297029 Cannot use mouse scroll wheel to change Via Row/Column field in Property Editor in IC6.1.6 ISR7
1296486 OASIS_Simulation_Interface license error leads to incorrect result in SGE distributed Parametric simulation
1296368 Copy library not referencing new library cells.
1296220 Request of EAD setup loading time improvement
1295804 vfoGuardRing.ils is not automatically loaded by 'virtuoso -nograph'.
1295745 VPS: Importing of results missing all the parasitics in the result form
1295592 emirreport gives failed to run command line error for EM
1295370 Blank Edit Object Properties form
1293281 DRD misses some minExtensionToCorner spacing violations
1293051 Cannot change width mode consistently in IC6.1.6 ISR6
1292884 Create Via Form: Unable to change via justification (center-center) in Width/Height Mode
1292881 DRD no longer detects minExtensionToCorner spacings
1292793 ADE XL cannot retain job policy assignment on the test that is not selected
1292548 Fit Y to Visible X has wrong functionality
1292440 EAD high precision extractor does not calculate total resistance correctly
1292382 Exactly overlapping shapes in different hierarchy should be treated as one by Pad Opening Info
1291775 For advanced processes, the EAD extractor is not checking for vertically overlapping shapes
1291176 MPS_ERROR when using EAD with third-party simulator
1290357 Performing yank and paste using SKILL code in IC6.1.6 ISR6 yields different results from previous IC6.1.x versions
1290173 dptReColor() indefinitely activates and deactivates coloring engine in loop
1289951 Received *Error* difference: can't handle (nil - 2) when open a new library from CIW File -> New -> Library
1289886 Placement Planning does not insert cap cell
1289869 addToExportList causes Virtuoso to crash
1289527 Display name for 'groundCap' parameter is 'Decoupled Capacitance' for Max Capacitance constraint.
1289132 EAD cannot read EM Data File format as same as VPS correctly
1288689 DRD Compactor crashes with small bus example
1288371 router crashes when setting rdeEval("setvar db.ignore_layers CSP")
1288358 DRD checker not checking for minExtensionEdge rule
1288055 Create Via claims: Mask numbers not as expected in std via def RX_sub
1288051 DPT recoloring claims: Mask numbers not as expected in std via def RX_sub
1287824 keepout errors post routing
1287789 eol spacing errors post routing
1287644 VPSML attempts to read EM rule file from an incorrect path
1287348 DRD compactor generates minCutClassSpacing violations
1287333 Overlapping pads counted twice in IC6.1.6 ISR6
1286955 ADE XL 12.1: Wrong job policy setting for inactive test
1286347 ignoreDesignChangesDuringRun not using global design variables with ams designer
1286161 Design analysis markers inadvertently removed from Annotation Browser when Routability Checker is run
1285985 VPSML and emirreport crash with 16FFp qrcTechFile
1285488 DPT GUI shows wrong color on the layers for stdVias in ICADV12.1 ISR8
1285430 emirreport issues when using autorun=true in post USR1 builds
1285268 Unable to visualize IDC current in EAD dataset for third-party simulator
1284805 vpsbatch does not finish em processing
1284644 Congestion Map should be affected from wide nets constraints
1284158 Random crashing when running check and save
1284146 In ADE XL, AMSD does not change model sections over corners when using ignoreDesignChangesDuringRun
1284093 VerilogOut: logical verilog does not work with the merge all option
1283724 In IC6.1.6, defout missing flattened vias
1283577 Data not properly populated in the "Waveform Signal" GUI when using amsDMV in conjunction with an ADE XL state with corners defined
1283079 CRASH: VSR crash when star_route called twice on same net with create_fromto
1282772 In IC6.1.6 ISR6, Virtuoso crashes while running distributed processing simulations in LSF mode
1282675 When AMS UNL views ADE XL simulation results, Irun log has suppressed compile and elaborate sections.
1282419 IC6.1.6: Virtuoso hangs at exit and CPU utilization hits 100%
1282066 Ability to turn off or ignore popup which comes when ignoreDesignChangesDuringRun is set and parameters exist
1281892 ncvlog illidn error with smg generated models
1281441 Router fails to route due to custom via definition for top layer
1281413 pteLoadFromTechFile causes selectability problems
1281351 QOR: getting multiple minWidth segments in star_route command.
1281121 stretch causes DRC violation
1280724 Wire Assistant doesn't appear with _iaGetOverrideEnabled error
1280678 incremental netlistAndRun after a netlist failure is not generating bindings for multiview cell
1280663 IC6.1.6 ISR6: Modgen recognizes the oaText
1280623 IC6.1.6 ISR6: Virtuoso crashes when using the Create Wire command
1280591 preRun trigger emission must occur before anything else in run flow
1280298 Router centers via1 on m1 pins causing DRC errors
1279996 VPS: Design resistors are listed under VSS pin in the EM report
1279908 runams with netlist command requires OASIS license
1279746 ADE XL crashes when copying and pasting multiple outputs
1279702 VPS is not able to process Recovery factor (em_recover) from ictfile
1279305 Copying of an expression to multiple expressions of another test leads to crash
1279279 Pin To Trunk routing results in long poly wire segments
1279122 Wire editing swaps "top" and "bottom" layers of wire assistant
1279071 Fast R extractor has some problems in the mesh wiring.
1278965 Provide ability to plot from Isignal icon in EAD results tab
1278961 If no tran analysis is run, we should not show Isignal in EAD results tab
1278498 Pin check for schematic has more pins than symbol with schematic switch master
1278477 Pin check for schematic has more bus pins than symbol
1278466 Pin check for schematic and text with more pins than symbol should fail at netlisting
1278411 Concat bus MM switchmaster functional gives false positive pin check
1278410 Concat with bit select switchmaster functional gives false positive pin check
1278397 Concat switchmaster functional gives false positive pin check
1278353 Provide SKILL API for Palette User Triggers
1277936 Virtuoso does not exit from CIW menu
1277891 crash in wsGraphSelectionState
1277877 DRD reports a dual pattern odd-loop on a Triple Patterning layer
1277870 The shielding constraint tandem (below) and coaxial should not use poly
1277530 VLS XL crash during generate all from source with extractor on
1277364 The waveform cannot be plotted when the wave name is 12345.trn.
1277152 Item selection callback is not working in IC6.1.6 if the callback function is defined within procedure.
1277090 DRD reports false twoWidths spacing violations causing the color engine to fail
1277064 libManager crashes if the cdslck files cannot be read
1276457 Auto Via Draw Area mode caused VLS hang
1276436 PIEA extraction should not stop with error CPF-1615
1275818 P2T routing with pin strapping causes DRC violation
1275565 Layout connectivity extractor should ignore stampLabelLayer function and mask number
1275323 Generic modgen routing is not inserting vias in few areas of the MODGEN routing
1275315 PreCreateObj triggered for ddViewFileType after ddCreateObj has been canceled
1275313 Routing IDE warning: Mask numbers not as expected in std via def RX_sub
1274830 Abstract is changing scan sigType to signal during pins step
1274016 VSR does not complete routes when there are blockages of type 'fill'
1273483 Reinitialize does not change modgen to status placed
1272999 rapidIP3 from AC analysis plot shows all power points
1272951 Setting the accessEdgesOn variable causes excessive memory use when panning
1272794 PIEA extraction takes very long with pushPGNetTypes enabled
1272670 GENERIC section not printed by VHDL netlister when hnlVHDLExternalDirList is used
1272007 Virtuoso Layout crashes when DRD form accessed
1271662 Quick Align fail for T-type path when auto-merge is allowed in any stretch like operation
1271507 bus_route does not complete routing on this bus
1271106 Via alignment to wire edge not obeyed in some cases
1271021 In IC6.1.6_ISR6, All Pins Optimization gives incorrect error about not enough space
1270769 DRD fails to correctly display minCutClass spacing violations
1270761 DRD rule text is always unreadable
1270620 proute_via_insertion results in minEdge failures
1270586 Update Components and Nets caused Modgens to move
1270547 Circuit Prospector filter for (un)constrained objects does not work properly
1270464 Sensitivity Analysis for uniform distribution models only uses half the specified range
1270186 tracef(t) produces extra information in IC6.1.6 release
1270161 Give more meaningful error message for HspiceD
1269762 In VLS XL, probe with Bus Bits Net Class is not highlighted
1269654 Crash when routing Point-to-Point with Color Track Patterns
1269590 Pin to Trunk router creates DRC violations if pre-placed vias or MPPs on pins already exists
1268817 data.dm in destination library is left in Checked Out state after copying a cell under SOS environment
1268569 Voltage source region cannot be created due to /tmp/ZeroDropInst file
1268532 Stretch FGR results in an unexpected location
1267690 noiseSummary command is not creating the noise summary file
1267333 The Results - Violations Display command hangs ADE environment
1267207 Some source fromtos created with minWidth during star routing
1267093 Cover obstruction on lower layers prevents the router from seeing shapes on upper layers
1266776 UNL: Improve the error message that appears when an invalid AMS simulator option is specified in ADE results
1266758 VPSML Connecting lines between violation markers are missing in IC6.1.6 ISR6
1266692 OASIS_Simulation_Interface license error
1266552 Improve the tapering at sink instance pin during star routing
1266192 Extend verilogIn maximum port size
1265785 Create autoVia with viaFillEnclosureOverlap ON did not fill up the overlapped area
1265754 Enhance Layer Palette search filter to scroll to the selected active layer automatically
1265135 stimulus file cannot be found using AMS designer and environment variable
1265058 vsabatch cannot copy the complete database to a result directory for vsaplot display
1264886 differences in check_routing_shape and check_vias results for allowedCutClass constraint checking
1264650 STAR routing to handle multiple pins/shapes per terminal
1264167 saveGraphImage does not wait for plotting to be displayed completely
1264112 In IC6.1.6, batch job fails if no "res=" values in emDataFile
1263977 pR-view bug for the current colorMap bar
1263845 modgen instances are placed offgrid with respect to global grid when mirrored
1263478 Cannot return to top layout by using Edit->Hierarchy->Return
1263156 Getting "*Error* system: operating system error occurred in execl: 7" error on displaying netlist
1262483 Via alignment is switched to center-center after Stretch command
1262399 power via insertion failing in hierarchical mode
1261253 VPS L attempts to checkout VPS XL license at 28nm EM analysis
1260974 viewing depth option should support negative depth
1260531 Use consistent terminology in all 'Function' rows and columns"
1260022 VCP is not placing instances whose masters do not have any geometry other than prBoundary
1260013 support triple height standard cell or more in VCP
1260007 An internal error on invoking reshape
1259971 The Create Via form retains the value of the Filter field
1259210 pull down and pop-up menus disappear when moving the mouse
1258960 Order of attribute of Edit Cellview Properties form should be lib/cell/view
1258791 AutoVia feature creates spacing violations for intermediate layers
1258298 vfo file load issue - CDLOut/ 3rd party tools .ils files are order dependent
1258240 CPF import miss gnd netSets
1257808 Virtuoso hangs after hiQuit()
1256468 ADE XL: result of Violations Display is incomplete when the Print command is clicked twice
1256391 Unexplained layerStackIsValid warning for mimcap layers
1254813 ADE not saving changes to Additional Arguments field in ADE L state
1253511 Syntax error on parsing emDataFile: Unexpected '='
1252565 Cannot create a Stack Via with more than 1000 rows
1252151 Crash after ADEXL-1625 message
1251037 all twigs on one instTerm need to be routed
1250094 SMG not generating the model for single index name at the instance pin
1248139 Need module name update for text cellviews when Update Instances is used
1247004 modify DRD to handle minArea and minRectArea
1246637 Create autovia with Extend Enclosure Beyond Overlap option caused edge length DRC violations
1246261 VPS to validate the input requirements
1246162 Changing the user or effective CDF is changing the base CDF also
1245930 verilogIn imports schematic OK first time; errors when run second time
1245697 Bindkey not working when Customize Range of Set Range section is set to min value & max value
1245692 Zoom-In of vsaplot should display all the data of specified region
1245632 vfpCPHGenPhysicalHierNoPropFile() should not generate unplaced instances
1245106 vsaplot should support results display same as results window
1244000 "Auto Via should merge the overlap area and then partition and fill the via
1243951 Modify Corner for chamfer on rectangle shapes in 16nm created non-45 angles
1243639 Need an option to control merging during Autovia generation
1243315 viaTriggers not working accurately
1241852 DRD reports sameMask spacing violations on stitched fixed loops
1241763 simulation tool environment settings cause context file to be loaded incorrectly.
1241718 Schematic property form gets updated with values from layout property form
1240577 VPS ML: Markers on layout disappear when zooming in
1239001 Checker is flagging false errors in 16nm data
1237164 Multipart path not redrawing with multiple edits in SKILL
1236617 Unable to retrieve corner/sweep point data with pss/pnoise in ADE XL
1236129 OASIS_Simulation_Interface license error when using Spectre simulator from ADE
1235993 asterisk(*) at the beginning of the parameters line in the spectre netlist causes errors
1235599 Routability Checker needs option to flag pins on incorrect side of prBoundary for selected routing direction
1234892 When Modgen is created in the schematic, trunks inside Modgen are decomposed
1233314 Trunk to Trunk is slow
1233289 Trunk to Trunk connects to twig metal, not to trunk
1231683 OASIS_Simulation_Interface license error when using Spectre simulator from ADE
1228387 Minimum requirement for metals is smaller than the actual metal width for errors
1227523 leEditInPlace command deletes VLS XL Gen From Source data
1227020 Unable to plot in PSFXL format during simulation with compression ON
1225109 Missing CDF Parameters in Edit Object Properties form
1224283 Cannot plot from ADE XL for AMS with Save times
1221334 ampersand used in CDF parameter prompt is displayed as amp; in Edit Object Properties form
1220633 Router fails to plan channels properly when constraints require mix of widths
1216301 update_power_domain specified incorrectly in exported CPF
1216295 PG nets not read completely from CPF
1212948 Even if the Route option is enabled, Routing is not done when the Generic Modgen is created.
1210593 ADE XL deletes contents of test editor if simulation fails
1200651 VSR router creates redundant vias over existing connections
1200385 Missing CDF Parameters in Edit Object Properties Form
1199726 DRD detects false twoWidths spacing violations
1199087 amsDMV unable to open results dumped by pure digital simulation
1197493 ADE XL crashes when copying and pasting multiple outputs
1195392 Signal name mapping issue when signal name prefix is the same as the top level testbench
1195199 Specifying 10K instances for mismatch crashes ADE XL Monte Carlo
1191768 CV2CV generates illegal terminal name for functional view.
1186752 Finish wire makes extra extension with taper pin width option
1182890 QoR issues with Modgen pin to trunk router
1179637 VHDL Toolbox netlisting fails with ".:schematic' is not a stopping cell"
1172401 create wire results in minEdgeAdjacentLength violation during via addition
1171978 Cluster and Modgen generated guardring based on different layer
1167850 Create Via creates allowedWidthRanges violations because of 1000 dbuPerUU
1159467 saveGraphImage has incorrect zoom
1158078 Changing the pattern changes the spacing between rows
1091554 Netlist not created for MonteCarlo with DUT and simulation remains in pending status
1090946 VLS XL Update Schematic Parameters destroys some field of the Edit Properties Form (schematic side)
1082020 useTrueBBox is not effective for mosaic
1072567 ADE XL Monte Carlo Specify Instances for Mismatch Generates Bad Netlist / Virtuoso: free(): invalid pointer
1054842 adding "selectable Contact Rows" as an option to "Guard Ring Options" UI
1045083 Copy cell with Update Instances ON does not update the module name
1034623 Via maximization is not effective
1029397 Waveform snapshot is broken when CPU is highly used
988260 Incorrect Via center calculation
971060 Edit Object Properties form: CDF parameter fields goes blank
918144 Schematic Property Editor is not displaying the CDF parameter section
915930 /tmp/.X11-unix/X file is not removed sometimes
855908 Edit Object Properties form goes blank when Update Layout Parameters command is run on a symbol
718511 Missing component properties in schematic window
611368 CDF missing from Edit Object Properties form
601269 Edit Object Properties form - CDF section is blank
519711 Schematic query form corrupted when layout query form open
474082 Blank CDF panel in schematic Object Properties form
472258 request to document schCleanObjectProp function
469685 CDF parameter is not displayed in schematic properties form
427821 VLS XL Cross probing results in missing CDF in Schematic Property Editor
262971 The CDF parameter is not updated correctly.
190272 Schematic Property Editor data getting updated to layout
42580 CDF parameters in the Edit Object Properties form disappear
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry.
Name: Cadence Virtuoso
Version: IC6.1.6 ISR8
Home: www.cadence.com
Interface: english
OS: Linux
Size: 9.7 Gb
Note: The IC6.1.6 FCS (base) version of Virtuoso was released in May 2013. The ISR stream is a cumulative stream of all hotfixes submitted since then.
Cadence Virtuoso version IC6.1.6 ISR8
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