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Cadence SPB OrCAD 16.60.014 Hotfix

Posted By: scutter
Cadence SPB OrCAD 16.60.014 Hotfix

Cadence SPB OrCAD 16.60.014 Hotfix | 813.5 mb

Cadence Design Systems, Inc. announce hotfix version 014 for 16.60 release. This update includes some critical bug fixes. Cadence Design Systems, Inc., a leader in global electronic design innovation, launched the Cadence OrCAD 16.6 design solution with new features, enhanced customization capabilities, and 20 percent simulation performance improvements that provide customers a shorter, more predictable path to product creation.

This latest release offers numerous improvements to tool usability and performance, but at the heart of 16.6 are three key benefits: enhanced miniaturization capabilities, timing-aware physical implementation and verification for faster timing closure, and the industry’s first electrical CAD team collaboration environment for PCB design using Microsoft SharePoint technology.

==========================================================================================
CCRID PRODUCT PRODUCTLEVEL2 TITLE
=============================================================================================
1155569 APD MODULES P1_U1 and P1_U3 Die pins are missing after Place Module.
1158528 CONCEPT_HDL OTHER Dual Monitor issue: Retain Hard Packaging option is missing and attribute test distorted
1160968 ALLEGRO_EDITOR SKILL Text Subclass change difference in Edit > Change and axlChangeLayer Skill command
1161986 SIG_INTEGRITY SIMULATION Flatline waveform seen when via model is set to detailed closed form or analytical solution
1162323 SIP_LAYOUT DIE_EDITOR Die Editor is incorrectly leaving an unassigned function pin in the die during refresh from die abstract
1162752 ALLEGRO_EDITOR SKILL axlDBChangeText doesnt recognize ?layer as a valid argument as documented
1165002 GRE CORE GRE Crashes during Plan Spatial giving "Memory Allocation Failure" Error.
1165469 CONCEPT_HDL CORE Import Design loses design library name
1165708 ALLEGRO_EDITOR TESTPREP Test point router failing when attempting to insert new TP via's
1165801 CONCEPT_HDL PDF Pin texts of spun symbol overlap in publish PDF.
1166020 SIP_LAYOUT WIREBOND Bondpads created with shapes do not follow the orthogonal pattern when adding wirebonds.
1166371 ALLEGRO_EDITOR DATABASE File locked for writing in 16.5 cannot be unlocked in 16.6
1166482 ALLEGRO_EDITOR INTERFACES Step orientation for y-rotated component is not exported correctly.
1167519 ALLEGRO_EDITOR DATABASE Uprev dbdoctor does not log warnings about renaming properties.
1167588 SIP_LAYOUT DIE_ABSTRACT_IF do not create a new pad stack for each I/O pad
1168496 ALLEGRO_EDITOR SCHEM_FTB Export Physical Crashes when netreving the board
1169510 SIP_LAYOUT WIZARDS Netlist in Wizard is crashing with this text file where the Net Name for one of the assignments is blank, meaning dummy
1169593 CONCEPT_HDL PDF Published PDF file's hyperlinks do not work fine when user click 1D10 or 2A10.
1169984 F2B PACKAGERXL Error Mapping cset when packaging but not in CM Audit
1171008 SIP_LAYOUT OTHER SiP Layout - Beta feature Void Adjacent Layer Shapes - changes or modifies "priority" of other/all shapes
1171411 ALLEGRO_EDITOR OTHER Enh - Break in Step 3D view in latest hotfix v16.6s013

A hot fix is a software maintenance package containing a small number of code fixes, designed to fix a sall number of critical problems. A hot fix enables a customer to receive fixes for urgent problems, without having to wait for the next service pack.

Each successive Fix Pack is comprehensive and contains the material from the earlier Fix Packs for that Release, as well as all Interim Fixes made available since the previous Fix Pack or full Release. In other words, when multiple Fix Packs are available, you would not need to apply Fix Pack 1 before applying Fix Pack 2.

About Cadence Design Systems, Inc.

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.

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Name: Cadence SPB OrCAD
Version: (32bit) 16.60.014 Hotfix
Home: www.cadence.com
Interface: english
OS: Windows XP / Vista / Seven
System Requirements: Cadence SPB OrCAD 16.60.000 - 16.60.013
Size: 813.5 mb

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