Cadence SPB OrCAD 16.5.033 (Allegro SPB) Hotfix
Cadence SPB OrCAD 16.5.033 (Allegro SPB) Hotfix | 667.2 mb
Cadence OrCAD PCB design suites combine industry-leading, production-proven, and highly scalable PCB design applications to deliver complete schematic entry, simulation, and place-and-route solutions. With these powerful, intuitive tools that integrate seamlessly across the entire PCB design flow, engineers can quickly move products from conception to final output.
To stay competitive in today’s market, companies must move their designs from engineering to manufacturing within ever-shrinking design schedules. Available as standalone products or in comprehensive suites, Cadence OrCAD personal productivity tools have a long history of addressing PCB design challenges, whether simple or complex. The powerful, tightly integrated PCB design technologies include OrCAD Capture for schematic design, various librarian tools, OrCAD PCB Editor for place and route, PSpice A/D for circuit simulation, OrCAD PCB SI for signal integrity analysis, and SPECCTRA for OrCAD for automatic routing. Easy to use and intuitive, these tools bring exceptional value and future-proof scalability to the Cadence Allegro system interconnect design platform to grow with future design demands. OrCAD PCB design suites provide integrated front-end design and simulation technology (Cadence OrCAD EE Designer) as well as an integrated back-end place-and-route design solution (Cadence OrCAD PCB Designer) to b ost productivity and accelerate time to market.
DATE: 10-31-2012 HOTFIX VERSION: 033
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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103395 COBALT-COMPILE COMPILE et3compile fails if compile for 3 boards in 32bit mode
715653 PSPICE MODELEDITOR Change in pin number assignment with model import for capture symbol
745682 CONCEPT_HDL CORE Attributes window requires resizing each time DEHDL is launched
825846 CONCEPT_HDL CORE The module_order.dat file gets corrupted
846658 CONCEPT_HDL CORE About Change the NOTE with DE-HDL
938977 CONCEPT_HDL CORE Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic
942044 CONCEPT_HDL CORE ConceptHDL crashes while opening the AMS project
946640 CONCEPT_HDL CORE Import Design should inherit module order defined in the imported block
968646 ALLEGRO_EDITOR EDIT_ETCH The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing
969535 CONSTRAINT_MGR SCM ASA retains information in the DCF file for parts/blocks that have been deleted and this causes problems.
976723 ADW MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor
981767 SCM UI Add series termination in ASA will crash if both output and input pins are selected.
988355 PCB_LIBRARIAN CORE PDV moving line-dot pinshapes left to right or visa versa places pintext wrongly
988438 CONCEPT_HDL CORE Visible constraint disrupts MOVE command
993562 CONCEPT_HDL INFRA After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).
996577 SPECCTRA ROUTE Specctra not routing NET_SHORT connections
997992 CONCEPT_HDL CORE Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?
1001300 PSPICE MODELEDITOR BUG: Simserver crash with encryptedm model
1006400 SCM OTHER Incorrect warning in SCM due to way voltage value is stored in tabular and schematic blocks
1011502 CONCEPT_HDL CORE Undo has an error on circle in DE-HDL during create a schematic symbol
1011798 ADW LIBDISTRIBUTION generate a differential report on parts in DB vs parts in PTF while running lib_dist
1012685 SIG_EXPLORER INTERACTIV SigXP: traceEtchFactor value is not used.
1013656 SCM OTHER create diff-pair should honour diff-pair setup or ask user for positive negative leg
1013721 ALLEGRO_EDITOR EDIT_ETCH Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.
1014319 CONCEPT_HDL CORE renaming HBlocks leads to crash
1017724 ADW TDA TDO update should force the schematic to re-read data from disk
1018506 ALLEGRO_EDITOR INTERACTIV Edit copy with retain net of via will assign net to pin
1019979 SIG_INTEGRITY LICENSING extracta batch command result is incorrect
1020746 CONCEPT_HDL OTHER PDF Publisher tool behavior inconsistent between OSs
1023051 SCM UI Wrong and incorrect message is generated while adding connectivity in SCM matrix view ї DSTABLE-140
1023057 CONCEPT_HDL CORE Strange message when opening DE-HDL - INFO(SPCOCN-2055)
1023281 PSPICE AA_PPLOT Bug:Pspice advance analysis pararmetric plotter stops after 6000+ runs
1023702 CAPTURE GENERAL ORCAD Capture/CIS copy and past page to other design Issue
1023807 SPECCTRA GUI Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button
1024890 PCB_LIBRARIAN METADATA con2con -metadataonly does not find footprints
1024899 PCB_LIBRARIAN CORE PDV symbol pins grid select all does not respect the filtering
1027147 CIS UPDATE_PART_STAT CIS gives ERROR(ORCIS-6274) when updating Part status from Part Manager
1028237 CONCEPT_HDL HDLDIRECT Error binding design when generating simulation netlist
1028432 SIP_LAYOUT DIE_ABSTRACT_IF Support pin numbers in die abstract flow
1029369 PDN_ANALYSIS EMVIEWER EMViewer: Unit of Current Density.
1030591 CAPTURE LIBRARY Library Correction utiltiy locks the library and deosn't frees it even after being closed
1031474 CONCEPT_HDL ARCHIVER Uisng Gtar as the compression utility causes the 'delete archive' to fail
1031765 PCB_LIBRARIAN OTHER librarian_expert feature is kept checked out for two hours
1032703 F2B DESIGNVARI Enhancement Replace Variant Component form needs to be resizeable
1033607 CAPTURE NETGROUPS Capture crash if netgroup instance name has square bracket ї[ї
1033853 SIG_INTEGRITY OTHER netrev crashes when importing logic
1035624 CONCEPT_HDL CORE Options pre-selected when launching base product
1036580 ALLEGRO_EDITOR MODULES Module created from completely routed board file has lot of missing connections in it.
1037345 ALLEGRO_EDITOR INTERACTIV Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)
1038180 ALLEGRO_EDITOR DRC_CONSTR BGA escapes not being calculated in phase tol
1038285 SCM UI Restore the option to launch DE-HDL after schgen.
1039147 ALLEGRO_EDITOR COLOR Need an option to change color of Text marker and Text select in Display listing
1040257 CONCEPT_HDL INFRA New license files causing slow tool performance
1040575 CIS CONFIGURATION SQL database views are not visible in CIS configuration step 2.
1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart
1040869 CONCEPT_HDL INFRA About uprev problems to SPB16.5 from 15.7
1040976 PCB_LIBRARIAN CORE PDV replace pinshape on Linux shows very slow performance compared to Windows
1042603 PSPICE SLPS About SLPS simulation interrupt
1042695 CIS CONFIGURATION Can't see database views of an SQL database in CIS configuration
1043339 CONCEPT_HDL PAGE_MGMT The .con and .xcon files aren't being updated.
1044029 PSPICE ENCRYPTION Encrypted lib not working for attached
1044222 ALLEGRO_EDITOR INTERACTIV Capture Canvas Image changes working directory
1044264 PSPICE SIMULATOR Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.
1045607 ALLEGRO_EDITOR OTHER Component get placed even after Cancel IDF in form.
1045609 ALLEGRO_EDITOR PLACEMENT Statement in the Viewlog for Update Symbol needs correction
1045694 CONCEPT_HDL INFRA Why to package the design twice to pass the net_short property to the board?
1045734 ALLEGRO_EDITOR OTHER Missing padstacks and layers information in cross section chart
1046929 CONSTRAINT_MGR OTHER Unable to create physical of spacing cset after rename the default cset in design entry.
1047361 CONSTRAINT_MGR OTHER CM fails to convert static phase tolerance value to database units.
1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll
1047823 CONSTRAINT_MGR OTHER acPutValue predicate text not being displayed at bottom of Constraint Manager window.
1047869 CONCEPT_HDL CORE How do I define a custom pwr/gnd symbol for correct Verilog syntax?
1049303 CONCEPT_HDL CORE Block rename deletes schematic data immediately in 16.5
1049317 CONCEPT_HDL OTHER bomhdl with scm mode not working on RHEL in 16.5
1049399 SIG_INTEGRITY OTHER Toggling z-axis delay in CM shows the same value
1049993 ALLEGRO_EDITOR EDIT_ETCH Loss of Y axis when adding via in manual group routing
1050483 ALLEGRO_EDITOR DRC_CONSTR DRC has been waived but after updated DRC system generated a new DRC.
1051588 ALLEGRO_EDITOR PAD_EDITOR Pad_Designer library drill report omits some drill holes
1052005 SIG_INTEGRITY OTHER Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.
1052056 ALLEGRO_EDITOR PADS_IN Pads to Allegro translator fails with error message "PARSE ERROR: Wrong label format:Translation aborted."
1052449 CONCEPT_HDL COPY_PROJECT Copy Project does not update all relative paths in the cpm file
1052479 PSPICE PROBE Cursor2 (Y2) displays the same value for all traces
1052753 ALLEGRO_EDITOR DRC_CONSTR Allegro showing soldermask drc only when the symbol is rotated.
1052817 CONCEPT_HDL CORE Getting packager error after renaming nets
1053319 CONCEPT_HDL INFRA Change in property scope in windows mode is not retained
1053602 CONCEPT_HDL OTHER Using the attached .NDX/DML files causes a lot of delay in invoking Tools > Model Assignment.
1053660 CAPTURE PROJECT_MANAGER Find Part Pin name or number is not working
1054010 CONCEPT_HDL CORE MAKE_BASE
1054235 ALLEGRO_EDITOR PLACEMENT Cannot place alt_symbols for mechanical parts.
1054846 CAPTURE PROJECT_MANAGER Crash on pressing Esc key
1055328 CONCEPT_HDL COPY_PROJECT Project Manager - Project Copy
1055729 CIS GEN_BOM Standard CIS BOM per page is not working correctly with option Process Selection
1056418 ALLEGRO_EDITOR OTHER PDF exports the blank text markers whether or not the markers are visible.
1057003 ALLEGRO_EDITOR SHAPE Z-copy to create RKI does not follow board outline
1057976 ALLEGRO_EDITOR DRC_CONSTR No Same net Spacing DRC on attached design.
1058364 ALLEGRO_EDITOR SKILL axlTransformObject() is moving refdes text when only symbol pin is selected for move
1058940 ALLEGRO_EDITOR INTERFACES IDF(PTC) out command output wrong angle value
1059901 CONCEPT_HDL CORE Global Property Change and <<OCC_DELETED>> property value.
1060428 CONCEPT_HDL CORE ADW Flow Manager Copy Project fails to complete
1060589 F2B PACKAGERXL Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.
1061172 CONCEPT_HDL CORE Unable to delete Voltage
1061424 CONCEPT_HDL CORE Customer creates <<OCC_DELETED>> property values.
1061659 ALLEGRO_EDITOR DATABASE Unable to return drawing origin to 00
1062532 CONCEPT_HDL CONSTRAINT_MGR Our customer saw different DIFF_PAIR contentsevery time they invoke the Constraint manager.
1062558 APD DXF_IF If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation
1064707 CONCEPT_HDL CHECKPLUS Rules Checker core dumps on design
1065124 PCB_LIBRARIAN SETUP PTF properties cannot be deleted from the setup in PDV
1065745 SIP_LAYOUT DATABASE The logic assign net command crashes the application
1065860 ALLEGRO_EDITOR REPORTS Design crashes when running a padstack usage report
1066051 ALLEGRO_EDITOR TESTPREP Auto Testprep generation creates TP with Testpoint to Component Locatin DRC
1066318 CONCEPT_HDL CREFER Issue with LOCATION visibility in flattened schematic
1068425 F2B DESIGNVARI Out of memory message in Variant Editor while їchange propertiesї command
1068966 SIP_LAYOUT DRC_CONSTRAINTS DRC update aborts on this design with ERROR -3000067
1069215 CAPTURE DATABASE Capture Crash on usnig a TCL utltiy to correct design
1069517 SIP_LAYOUT DIE_EDITOR change die abstract pins tab default action from delete to modify
===================================================================================================================================
CCRID PRODUCT PRODUCTLEVEL2 TITLE
===================================================================================================================================
103395 COBALT-COMPILE COMPILE et3compile fails if compile for 3 boards in 32bit mode
715653 PSPICE MODELEDITOR Change in pin number assignment with model import for capture symbol
745682 CONCEPT_HDL CORE Attributes window requires resizing each time DEHDL is launched
825846 CONCEPT_HDL CORE The module_order.dat file gets corrupted
846658 CONCEPT_HDL CORE About Change the NOTE with DE-HDL
938977 CONCEPT_HDL CORE Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic
942044 CONCEPT_HDL CORE ConceptHDL crashes while opening the AMS project
946640 CONCEPT_HDL CORE Import Design should inherit module order defined in the imported block
968646 ALLEGRO_EDITOR EDIT_ETCH The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing
969535 CONSTRAINT_MGR SCM ASA retains information in the DCF file for parts/blocks that have been deleted and this causes problems.
976723 ADW MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor
981767 SCM UI Add series termination in ASA will crash if both output and input pins are selected.
988355 PCB_LIBRARIAN CORE PDV moving line-dot pinshapes left to right or visa versa places pintext wrongly
988438 CONCEPT_HDL CORE Visible constraint disrupts MOVE command
993562 CONCEPT_HDL INFRA After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).
996577 SPECCTRA ROUTE Specctra not routing NET_SHORT connections
997992 CONCEPT_HDL CORE Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?
1001300 PSPICE MODELEDITOR BUG: Simserver crash with encryptedm model
1006400 SCM OTHER Incorrect warning in SCM due to way voltage value is stored in tabular and schematic blocks
1011502 CONCEPT_HDL CORE Undo has an error on circle in DE-HDL during create a schematic symbol
1011798 ADW LIBDISTRIBUTION generate a differential report on parts in DB vs parts in PTF while running lib_dist
1012685 SIG_EXPLORER INTERACTIV SigXP: traceEtchFactor value is not used.
1013656 SCM OTHER create diff-pair should honour diff-pair setup or ask user for positive negative leg
1013721 ALLEGRO_EDITOR EDIT_ETCH Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.
1014319 CONCEPT_HDL CORE renaming HBlocks leads to crash
1017724 ADW TDA TDO update should force the schematic to re-read data from disk
1018506 ALLEGRO_EDITOR INTERACTIV Edit copy with retain net of via will assign net to pin
1019979 SIG_INTEGRITY LICENSING extracta batch command result is incorrect
1020746 CONCEPT_HDL OTHER PDF Publisher tool behavior inconsistent between OSs
1023051 SCM UI Wrong and incorrect message is generated while adding connectivity in SCM matrix view ї DSTABLE-140
1023057 CONCEPT_HDL CORE Strange message when opening DE-HDL - INFO(SPCOCN-2055)
1023281 PSPICE AA_PPLOT Bug:Pspice advance analysis pararmetric plotter stops after 6000+ runs
1023702 CAPTURE GENERAL ORCAD Capture/CIS copy and past page to other design Issue
1023807 SPECCTRA GUI Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button
1024890 PCB_LIBRARIAN METADATA con2con -metadataonly does not find footprints
1024899 PCB_LIBRARIAN CORE PDV symbol pins grid select all does not respect the filtering
1027147 CIS UPDATE_PART_STAT CIS gives ERROR(ORCIS-6274) when updating Part status from Part Manager
1028237 CONCEPT_HDL HDLDIRECT Error binding design when generating simulation netlist
1028432 SIP_LAYOUT DIE_ABSTRACT_IF Support pin numbers in die abstract flow
1029369 PDN_ANALYSIS EMVIEWER EMViewer: Unit of Current Density.
1030591 CAPTURE LIBRARY Library Correction utiltiy locks the library and deosn't frees it even after being closed
1031474 CONCEPT_HDL ARCHIVER Uisng Gtar as the compression utility causes the 'delete archive' to fail
1031765 PCB_LIBRARIAN OTHER librarian_expert feature is kept checked out for two hours
1032703 F2B DESIGNVARI Enhancement Replace Variant Component form needs to be resizeable
1033607 CAPTURE NETGROUPS Capture crash if netgroup instance name has square bracket ї[ї
1033853 SIG_INTEGRITY OTHER netrev crashes when importing logic
1035624 CONCEPT_HDL CORE Options pre-selected when launching base product
1036580 ALLEGRO_EDITOR MODULES Module created from completely routed board file has lot of missing connections in it.
1037345 ALLEGRO_EDITOR INTERACTIV Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)
1038180 ALLEGRO_EDITOR DRC_CONSTR BGA escapes not being calculated in phase tol
1038285 SCM UI Restore the option to launch DE-HDL after schgen.
1039147 ALLEGRO_EDITOR COLOR Need an option to change color of Text marker and Text select in Display listing
1040257 CONCEPT_HDL INFRA New license files causing slow tool performance
1040575 CIS CONFIGURATION SQL database views are not visible in CIS configuration step 2.
1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart
1040869 CONCEPT_HDL INFRA About uprev problems to SPB16.5 from 15.7
1040976 PCB_LIBRARIAN CORE PDV replace pinshape on Linux shows very slow performance compared to Windows
1042603 PSPICE SLPS About SLPS simulation interrupt
1042695 CIS CONFIGURATION Can't see database views of an SQL database in CIS configuration
1043339 CONCEPT_HDL PAGE_MGMT The .con and .xcon files aren't being updated.
1044029 PSPICE ENCRYPTION Encrypted lib not working for attached
1044222 ALLEGRO_EDITOR INTERACTIV Capture Canvas Image changes working directory
1044264 PSPICE SIMULATOR Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.
1045607 ALLEGRO_EDITOR OTHER Component get placed even after Cancel IDF in form.
1045609 ALLEGRO_EDITOR PLACEMENT Statement in the Viewlog for Update Symbol needs correction
1045694 CONCEPT_HDL INFRA Why to package the design twice to pass the net_short property to the board?
1045734 ALLEGRO_EDITOR OTHER Missing padstacks and layers information in cross section chart
1046929 CONSTRAINT_MGR OTHER Unable to create physical of spacing cset after rename the default cset in design entry.
1047361 CONSTRAINT_MGR OTHER CM fails to convert static phase tolerance value to database units.
1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll
1047823 CONSTRAINT_MGR OTHER acPutValue predicate text not being displayed at bottom of Constraint Manager window.
1047869 CONCEPT_HDL CORE How do I define a custom pwr/gnd symbol for correct Verilog syntax?
1049303 CONCEPT_HDL CORE Block rename deletes schematic data immediately in 16.5
1049317 CONCEPT_HDL OTHER bomhdl with scm mode not working on RHEL in 16.5
1049399 SIG_INTEGRITY OTHER Toggling z-axis delay in CM shows the same value
1049993 ALLEGRO_EDITOR EDIT_ETCH Loss of Y axis when adding via in manual group routing
1050483 ALLEGRO_EDITOR DRC_CONSTR DRC has been waived but after updated DRC system generated a new DRC.
1051588 ALLEGRO_EDITOR PAD_EDITOR Pad_Designer library drill report omits some drill holes
1052005 SIG_INTEGRITY OTHER Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.
1052056 ALLEGRO_EDITOR PADS_IN Pads to Allegro translator fails with error message "PARSE ERROR: Wrong label format:Translation aborted."
1052449 CONCEPT_HDL COPY_PROJECT Copy Project does not update all relative paths in the cpm file
1052479 PSPICE PROBE Cursor2 (Y2) displays the same value for all traces
1052753 ALLEGRO_EDITOR DRC_CONSTR Allegro showing soldermask drc only when the symbol is rotated.
1052817 CONCEPT_HDL CORE Getting packager error after renaming nets
1053319 CONCEPT_HDL INFRA Change in property scope in windows mode is not retained
1053602 CONCEPT_HDL OTHER Using the attached .NDX/DML files causes a lot of delay in invoking Tools > Model Assignment.
1053660 CAPTURE PROJECT_MANAGER Find Part Pin name or number is not working
1054010 CONCEPT_HDL CORE MAKE_BASE
1054235 ALLEGRO_EDITOR PLACEMENT Cannot place alt_symbols for mechanical parts.
1054846 CAPTURE PROJECT_MANAGER Crash on pressing Esc key
1055328 CONCEPT_HDL COPY_PROJECT Project Manager - Project Copy
1055729 CIS GEN_BOM Standard CIS BOM per page is not working correctly with option Process Selection
1056418 ALLEGRO_EDITOR OTHER PDF exports the blank text markers whether or not the markers are visible.
1057003 ALLEGRO_EDITOR SHAPE Z-copy to create RKI does not follow board outline
1057976 ALLEGRO_EDITOR DRC_CONSTR No Same net Spacing DRC on attached design.
1058364 ALLEGRO_EDITOR SKILL axlTransformObject() is moving refdes text when only symbol pin is selected for move
1058940 ALLEGRO_EDITOR INTERFACES IDF(PTC) out command output wrong angle value
1059901 CONCEPT_HDL CORE Global Property Change and <<OCC_DELETED>> property value.
1060428 CONCEPT_HDL CORE ADW Flow Manager Copy Project fails to complete
1060589 F2B PACKAGERXL Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.
1061172 CONCEPT_HDL CORE Unable to delete Voltage
1061424 CONCEPT_HDL CORE Customer creates <<OCC_DELETED>> property values.
1061659 ALLEGRO_EDITOR DATABASE Unable to return drawing origin to 00
1062532 CONCEPT_HDL CONSTRAINT_MGR Our customer saw different DIFF_PAIR contentsevery time they invoke the Constraint manager.
1062558 APD DXF_IF If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation
1064707 CONCEPT_HDL CHECKPLUS Rules Checker core dumps on design
1065124 PCB_LIBRARIAN SETUP PTF properties cannot be deleted from the setup in PDV
1065745 SIP_LAYOUT DATABASE The logic assign net command crashes the application
1065860 ALLEGRO_EDITOR REPORTS Design crashes when running a padstack usage report
1066051 ALLEGRO_EDITOR TESTPREP Auto Testprep generation creates TP with Testpoint to Component Locatin DRC
1066318 CONCEPT_HDL CREFER Issue with LOCATION visibility in flattened schematic
1068425 F2B DESIGNVARI Out of memory message in Variant Editor while їchange propertiesї command
1068966 SIP_LAYOUT DRC_CONSTRAINTS DRC update aborts on this design with ERROR -3000067
1069215 CAPTURE DATABASE Capture Crash on usnig a TCL utltiy to correct design
1069517 SIP_LAYOUT DIE_EDITOR change die abstract pins tab default action from delete to modify
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Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
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Name: Cadence SPB OrCAD
Version: 16.5.033 (Allegro SPB) 32bit Hotfix
Creator: www.cadence.com
Interface: english
OS: Windows XP / Vista / Seven
System Requirements: Cadence SPB/OrCAD 16.50.000 - 16.50.032
OS: Windows XP / Vista / Seven
Size: 667.2 mb
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