Cadence SPB OrCAD 16.5.0(30)31 (Allegro SPB) Hotfix
Cadence SPB OrCAD 16.5.0(30)31 (Allegro SPB) Hotfix | 1.3 Gb
Cadence OrCAD PCB design suites combine industry-leading, production-proven, and highly scalable PCB design applications to deliver complete schematic entry, simulation, and place-and-route solutions. With these powerful, intuitive tools that integrate seamlessly across the entire PCB design flow, engineers can quickly move products from conception to final output.
To stay competitive in today’s market, companies must move their designs from engineering to manufacturing within ever-shrinking design schedules. Available as standalone products or in comprehensive suites, Cadence OrCAD personal productivity tools have a long history of addressing PCB design challenges, whether simple or complex. The powerful, tightly integrated PCB design technologies include OrCAD Capture for schematic design, various librarian tools, OrCAD PCB Editor for place and route, PSpice A/D for circuit simulation, OrCAD PCB SI for signal integrity analysis, and SPECCTRA for OrCAD for automatic routing. Easy to use and intuitive, these tools bring exceptional value and future-proof scalability to the Cadence Allegro system interconnect design platform to grow with future design demands. OrCAD PCB design suites provide integrated front-end design and simulation technology (Cadence OrCAD EE Designer) as well as an integrated back-end place-and-route design solution (Cadence OrCAD PCB Designer) to b ost productivity and accelerate time to market.
DATE: 10-5-2012 HOTFIX VERSION: 031
===================================================================================================================================
CCRID PRODUCT PRODUCTLEVEL2 TITLE
===================================================================================================================================
1044754 SIG_INTEGRITY SIMULATION Incorrect waveforms when simulating with stacked die
1053631 FSP DE-HDL_SCHEMATIC SchGen doesn't place DiffPairs together on the symbol
1054456 ALLEGRO_EDITOR MENTOR mbs2lib incorrectly translates refdes label
1054871 CONCEPT_HDL CORE Problem with creating schematic from block symbol
1055481 APD SHAPE keepout does not clear shape unless it's picked up and dropped down
DATE: 09-21-2012 HOTFIX VERSION: 030
===================================================================================================================================
CCRID PRODUCT PRODUCTLEVEL2 TITLE
===================================================================================================================================
1008113 FSP VIRTUAL_INTERFAC importing Altera constraints verilog to make virtual interface only small percentage of nets have IO standard
1042199 SIG_INTEGRITY SIMULATION Waveform list was not refreshed by switching tab.
1042348 SIP_LAYOUT STREAM_IF GDSII export includes the full refernce path, breaks CATS flow
1046527 ALLEGRO_EDITOR INTERACTIV Display Segment Over Void not working correctly.
1047590 ALLEGRO_EDITOR SCHEM_FTB Buses created in Allegro-CM are deleted by netrev in traditional flow
1047969 ALLEGRO_EDITOR NC Some route path missed in .rou file.
1048907 ALLEGRO_EDITOR OTHER PDF_OUT is very slow
1049262 ALLEGRO_EDITOR OTHER APD and extracta crash owing to Wirebond.
1050408 APD DXF_IF Symbol has 45 degrees rotation in mcm but DXF doesnїt.
1052045 ALLEGRO_EDITOR OTHER Bug - Thermal relief connects not sustaining 15 degrees component spin in version 16.5 unlike v16.3
1052600 ALLEGRO_EDITOR SHAPE Adding a specific cline causing shape errors
1053065 MODEL_EDITOR GUI The About ModelEditor form indicates an incorrect version.
1054008 CONCEPT_HDL CONSTRAINT_MGR Out of memory error while launching CM within DEHDL
1054269 ALLEGRO_EDITOR MANUFACT Backdrill Setup and Analysis crashes on attached design
1055273 ALLEGRO_EDITOR INTERFACES DXF exported from Allegro has an offset in pad location for Y- direction.
===================================================================================================================================
CCRID PRODUCT PRODUCTLEVEL2 TITLE
===================================================================================================================================
1044754 SIG_INTEGRITY SIMULATION Incorrect waveforms when simulating with stacked die
1053631 FSP DE-HDL_SCHEMATIC SchGen doesn't place DiffPairs together on the symbol
1054456 ALLEGRO_EDITOR MENTOR mbs2lib incorrectly translates refdes label
1054871 CONCEPT_HDL CORE Problem with creating schematic from block symbol
1055481 APD SHAPE keepout does not clear shape unless it's picked up and dropped down
DATE: 09-21-2012 HOTFIX VERSION: 030
===================================================================================================================================
CCRID PRODUCT PRODUCTLEVEL2 TITLE
===================================================================================================================================
1008113 FSP VIRTUAL_INTERFAC importing Altera constraints verilog to make virtual interface only small percentage of nets have IO standard
1042199 SIG_INTEGRITY SIMULATION Waveform list was not refreshed by switching tab.
1042348 SIP_LAYOUT STREAM_IF GDSII export includes the full refernce path, breaks CATS flow
1046527 ALLEGRO_EDITOR INTERACTIV Display Segment Over Void not working correctly.
1047590 ALLEGRO_EDITOR SCHEM_FTB Buses created in Allegro-CM are deleted by netrev in traditional flow
1047969 ALLEGRO_EDITOR NC Some route path missed in .rou file.
1048907 ALLEGRO_EDITOR OTHER PDF_OUT is very slow
1049262 ALLEGRO_EDITOR OTHER APD and extracta crash owing to Wirebond.
1050408 APD DXF_IF Symbol has 45 degrees rotation in mcm but DXF doesnїt.
1052045 ALLEGRO_EDITOR OTHER Bug - Thermal relief connects not sustaining 15 degrees component spin in version 16.5 unlike v16.3
1052600 ALLEGRO_EDITOR SHAPE Adding a specific cline causing shape errors
1053065 MODEL_EDITOR GUI The About ModelEditor form indicates an incorrect version.
1054008 CONCEPT_HDL CONSTRAINT_MGR Out of memory error while launching CM within DEHDL
1054269 ALLEGRO_EDITOR MANUFACT Backdrill Setup and Analysis crashes on attached design
1055273 ALLEGRO_EDITOR INTERFACES DXF exported from Allegro has an offset in pad location for Y- direction.
About Cadence Design Systems, Inc.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
visit my blog
Name: Cadence SPB OrCAD
Version: 16.5.0(30)31 (Allegro SPB) 32bit Hotfix
Creator: www.cadence.com
Interface: english
OS: Windows XP / Vista / Seven
System Requirements: Cadence SPB/OrCAD 16.50.000 - 16.50.029
OS: Windows XP / Vista / Seven
Size: 1.3 Gb
No mirrors please