Writing Testbenches using SystemVerilog { Repost }
Janick Bergeron, «Writing Testbenches using SystemVerilog»
Springer | ISBN : 0387292217 | 1 edition (February 10, 2006) | 414 pages | PDF | 2.5 Mb
Springer | ISBN : 0387292217 | 1 edition (February 10, 2006) | 414 pages | PDF | 2.5 Mb
Verification is too often approached in an ad hoc fashion. Visually inspecting simulation results is no longer feasible and the directed test-case methodology is reaching its limit. Moore's Law demands a productivity revolution in functional verification methodology. Writing Testbenches Using SystemVerilog offers a clear blueprint of a verification process that aims for first-time success using the SystemVerilog language. From simulators to source management tools, from specification to functional coverage, from I's and O's to high-level abstractions, from interfaces to bus-functional models, from transactions to self-checking testbenches, from directed testcases to constrained random generators, from behavioral models to regression suites, this book covers it all.